1. Field of the Invention
This invention relates to an electrically rewritable nonvolatile semiconductor memory device. Among nonvolatile semiconductor memories, it especially relates to a NAND type flash memory.
2. Description of Related Art
In recent years, the demand of small nonvolatile semiconductor memories with large capacity increases rapidly, and the NAND type flash memory which can expect high integration and large capacity has especially attracted attention, compared with the conventional NOR type flash memory.
For the purpose of manufacturing a NAND type flash memory with large capacity, chip shrink for high integration will be promoted. However, as chip shrink progresses, a bit line interval is shortened and the contiguity capacity of the bit line is getting large. These days, the contiguity bit line capacity has reached 80% of the whole bit line capacity. It is considered that as capacity of a flash memory becomes large, the chip shrink further progresses and the contiguity bit line capacity is going to be larger.
In the NAND type flash memory, in order to make the consumption current of sense amplifier (S/A) small, the “voltage sense method” which detects the electric charge of a bit line is adopted. The sense operation of the data in the NAND type flash memory of the voltage sense method is as follows.
(1) Store the electric charge in the bit line beforehand (precharge).
(2) When a NAND memory cell turns on, because the precharged electric charge passes through a NAND memory cell, the potential of the bit line becomes VSS (discharge).
(3) When the NAND memory cell does not turn on, because the precharged electric charge is not drawn out, the potential of the bit line is maintained as the precharged potential. In this case, the bit line is floating.
(4) At the time when the discharge ended, data is read by detecting the voltage level of the bit line with a sense amplifier.
Due to the fact that the chip shrink has progressed and the contiguity bit line capacity has become large in recent years, regarding the bit line adjoining the bit line in a floating state in the above-mentioned state of (3) (i.e. the state which the NAND memory cell does not turn on), when discharge of the bit line described in the above-mentioned (2) is performed, it is influenced by the contiguity capacity of the bit line and the potential of the bit line in floating also decreases. Thus, what is called “coupling” phenomenon arises. Originally, in the above-mentioned state of (3), the potential of the bit line should have maintained the precharged level. However, the potential of the bit line decreases due to the influence of coupling, and an incorrect sense is caused. Therefore, there is a case where it becomes impossible to perform exact read-out operation. In order to avoid the incorrect sense caused by the influence of this coupling, for example, the method of shielding an adjoining bit line is adopted these days, as indicated by U.S. Pat. No. 5,453,955.
In this method of shielding the adjoining bit line (hereinafter referred to as the “bit line shielding method”), one sense amplifier circuit (S/A and latch) is shared by two bit lines as shown in FIG. 1. That is, the adjoining bit lines are classified into even number (Even) and odd number (Odd), and the structure that the adjoining bit lines of even number and odd number share one sense amplifier is adopted.
In read-out operation of this bit line shielding method, when the data of the bit line of even number are read out (when even-numbered pages are read out), transfer gates for the even-bit lines (BLSe) are turned on, and the even-bit lines are connected to the sense amplifier. At this time, by turning on transistors for grounding (BIASo) the odd-bit lines are connected to BLCRL to become grounding potential (VSS). Under this state, if potential (VDD) is precharged from the sense amplifier (S/A) on the even-bit lines, since the potential of the odd-bit lines are held at VSS, the even-bit lines are not influenced by the odd-bit lines, and precharge is performed appropriately.
On the other hand, when reading the data of the odd-bit lines, the transfer gate for the odd-bit lines (BLSo) is turned on, and the odd-bit lines are connected to the sense amplifier. At this time, by turning on the transistor for grounding (BIASe), the even-bit lines are connected to BLCRL to make grounding potential (VSS). If the potential (VDD) is precharged from the sense amplifier (S/A) on the odd-bit lines under this state, since the potential of the even-bit lines are held at VSS, the odd-bit lines are not influenced by the even-bit lines, and precharge is performed appropriately.
Thus, in the bit line shielding method, by making the adjoining non-selected bit line into a grounding state at the time of read-out operation, it becomes possible to perform exact read-out operation, without being influenced by the signal of the adjoining bit line.
At the time of write-in operation of data (at the time of program operation), in order to speed up write-in speed, since the adjoining bit lines do not influence each other, it is desirable to write in the even-bit line and the odd-bit line simultaneously.
However, in the conventional NAND type flash memory using the bit line shielding method shown in FIG. 1, it is impossible to write in the even-bit lines and the odd-bit lines simultaneously due to a circuit structure. Therefore, it is necessary to write data to the even-bit lines and the odd-bit lines by turns at the time of writing data. On the other hand, the demand to speed up the NAND type flash memory in a market is increasing, it is desired to realize that the even-bit lines and the odd-bit lines are written in simultaneously and the whole system of the NAND type flash memory speeds up.